// single-port ram inference model

`timescale 1ns/1ps

module sp_ram
#(parameter
    DWIDTH = 8,
    DEPTH  = 256,
    AWIDTH = log2(DEPTH-1)
)
(
    input  wire              I_sclk,
    input  wire              I_ce,
    input  wire              I_we,
    input  wire [AWIDTH-1:0] I_addr,
    input  wire [DWIDTH-1:0] I_data,
    output wire [DWIDTH-1:0] O_q
);
//------------------------Parameter----------------------

//------------------------Local signal-------------------
reg  [DWIDTH-1:0] mem[0:DEPTH-1];
reg  [DWIDTH-1:0] q_buf;

//------------------------Instantiation------------------

//------------------------Task and function--------------
function integer log2;
    input  [ 31: 0] value;
    begin
    for (log2 = 0; value > 0; log2 = log2 + 1)
        value = value >> 1;
    end
endfunction

//------------------------Body---------------------------
assign O_q = q_buf;

always @(posedge I_sclk) begin
    if (I_ce) begin
        if (I_we)
            mem[I_addr] <= I_data;
        else
            q_buf <= mem[I_addr];
    end
end

endmodule

// vim:set tw=0 ts=4 sw=4 et:
